The present invention relates to a method for fabrication of a field effect transistor using a compound semiconductor.
The following explanation will be made taking a GaAs metal-semiconductor field effect transistor (hereinafter referred to as MESFET) as an example.
In order to suppress the fluctuations of a threshold voltage of a GaAs MESFET formed on a semi-insulating GaAs substrate and thereby to implement the improvement of performance including the reduction of a source resistance, there is widely employed a self-alignment FET in which n.sup.+ source and drain regions are formed through ion implantation and in self-alignment with a refractory metal gate. In recent years, there has been developed a GaAs MESFET called LDD (lightly doped drain) structure which includes a medium impurity concentration implanted layer called an n' layer between an implanted well layer and a usual n.sup.+ implanted layer and n' layer has an impurity concentration lower than that of the n.sup.+ layer, thereby improving a drain breakdown voltage. FIGS. 1a to 1g show a method for fabrication of an enhancement mode FET which is a typical example of such an LDD GaAs MESFET.
As shown in FIG. 1a, Si.sup.29 ions are selectively implanted at 30 KeV with a dose of 2.5.times.10.sup.12 cm.sup.-2 into one principal surface of a semi-insulating GaAs substrate 1 with a photoresist film 2 used as a mask, thereby forming an active layer 3. Next, as shown in FIG. 1b, a WSi.sub.0.6 film 18 (having a thickness of 2000 .ANG.) is formed on the entire surface of the structure through a sputtering method after removal of the photoresist film and a photolithography method is thereafter used to form a photoresist film 19 on a region which is to serve as a gate. Then, as shown in FIG. 1c, the WSi.sub.0.6 film 18 is subjected to anisotropic dry etching by use of a CF.sub.4 gas and with the photoresist film 19 used as a mask and the photoresist film mask is removed, thereby providing a gate electrode 4. Thereafter, as shown in FIG. 1d, a photoresist film 13 is formed and Si.sup.29 ions are implanted at 50 KeV with a dose of 6.times.10.sup.12 cm.sup.-2 into predetermined regions from the upside of the gate electrode with the photoresist film 13 used as a mask to form n' layers 5. In this case, the Si.sup.29 ions are not implanted into the active layer 3 just under the gate electrode 4.
Next, the photoresist film 13 is removed and an SiO.sub.2 film 6 having a thickness of 2000 .ANG. is thereafter formed on the entire surface of the resultant structure by means of a plasma enhanced CVD method, as shown in FIG. 1e. Then, a photoresist film 14 is deposited and Si.sup.28 ions are implanted at 160 KeV with a dose of 5.times.10.sup.13 cm.sup.-2 into predetermined regions through the SiO.sub.2 film 6 with the photoresist film 14 used as a mask to form n.sup.+ layers 7. In this case, since the SiO.sub.2 film on the side wall portion of the gate electrode is thick so that the Si.sup.28 ions are not implanted into the GaAs substrate, the n.sup.+ layer 7 is formed at a distance of the side wall width L.sub.s from the gate electrode. Next, the photoresist film 14 and the SiO.sub.2 film 6 are removed by use of a buffer HF solution or the like and an SiO.sub.2 film 8 is thereafter deposited with a thickness of about 1000 .ANG. on the surface of the structure by means of a thermal CVD method, as shown in FIG. 1f. The resultant structure is annealed at 800.degree. C. for 20 minutes in an Ar/AsH.sub.3 atmosphere, thereby activating the ion implanted regions. Next, as shown in FIG. 1g, predetermined portions of the SiO.sub.2 film 8 are opened to form therein ohmic electrodes 9 made of AuGeNi, thereby completing an FET.
However, in the conventional FET having the above-mentioned structure, since the n' and n.sup.+ implanted layers 5 and 7 serving as a source and a drain are formed symmetrically with respect to the gate electrode, there is a problem that an approach to further reduction in source resistance (R.sub.s) and to increase in transconductance (g.sub.m) causes the deterioration of a drain breakdown voltage and the increase of a drain conductance (g.sub.d) and a gate-drain capacitance (C.sub.gd), thereby deteriorating a high frequency characteristic and a drain voltage (V.sub.d) margin of the FET.
An example in which an asymmetric source/drain structure is provided in order to avoid the above-mentioned problem is shown in FIG. 4. FIG. 2 shows a fabrication process step substituted for the step of FIG. 1e in which the n.sup.+ layer 7 is formed. Si.sup.28 ions are implanted using a photoresist film 22 in such a manner that it selectively covers only a drain region in a manual alignment manner. Thereby, an n' implanted layer 25 and an n.sup.+ implanted layer 27 asymmetric with respect to gate electrode 24 are formed by the help of the photoresist film 22 partially provided on the surface. A source and a drain formed by the n' implanted layer 25 and the n.sup.+ implanted layer 27 can be individually adjusted so as to reduce a source resistance and to increase a transconductance. However, a control is required so that the position of an end portion R.sub.e of the photoresist film falls within a range of L.sub.R across the gate electrode 24, as shown in FIG. 2. Fine delineation of the FET encounters problems such as residue of resist in the source region and deviation of the mask relative to the electrode 24 having a short gate length.